oberheimmatrix1000
Differences
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| Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
| oberheimmatrix1000 [2016-07-30 05:53] – [6850 UART] gde | oberheimmatrix1000 [2016-09-26 20:21] (current) – [6850 UART] gde | ||
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| Gareth is working on a [[https:// | Gareth is working on a [[https:// | ||
| + | |||
| + | ==== Matrix 6/100 links ==== | ||
| + | |||
| + | http:// | ||
| + | |||
| + | http:// | ||
| + | |||
| + | http:// | ||
| + | |||
| ===== Memory Map ===== | ===== Memory Map ===== | ||
| Line 77: | Line 86: | ||
| 0x1400-0x17ff UORV* { | 0x1400-0x17ff UORV* { | ||
| | | ||
| - | 0x1400 - $ U809 - 68850 - UART (if A9 = 0) | + | 0x1400-0x15ff |
| - | 0x1600 - 82C54 Programmable Timer (if A9 = 1) | + | 0x1406 - Control/ |
| + | Control (write-only) { | ||
| + | Bit 0: Counter Divide Select 0 (CR0) | ||
| + | Bit 1: Counter Divide Select 1 (CR1) | ||
| + | Bit 2: Word Select 1 (CR2) | ||
| + | Bit 3: Word Select 2 (CR3) | ||
| + | Bit 4: Word Select 3 (CR4) | ||
| + | Bit 5: Transmit Control 1 (CR5) | ||
| + | Bit 6: Transmit Control 2 (CR6) | ||
| + | Bit 7: Receive Interrupt Enable (CR7) | ||
| + | } | ||
| + | Status (read-only) { | ||
| + | Bit 0: Receive Data Register Full (RDRF) | ||
| + | Bit 1: Transmit Data Register Empty (TDRE) | ||
| + | Bit 2: Data Carrier Detect (/DCD) active low | ||
| + | Bit 3: Clear To Send (/CTS) active low | ||
| + | Bit 4: Framing error (FE) | ||
| + | Bit 5: Receiver Overrun (OVRN) | ||
| + | Bit 6: Parity Error (PE) | ||
| + | Bit 7: Interrupt Request (IRQ) | ||
| + | } | ||
| + | } | ||
| + | 0x1407 - Transmit/ | ||
| + | } | ||
| + | 0x1600 - 82C54 Programmable Timer (if A9 = 1) { | ||
| This timer is the source of /IRQ back to the 6809 | This timer is the source of /IRQ back to the 6809 | ||
| + | 0x1600 - Counter 0 Register | ||
| + | 0x1601 - Counter 1 Register | ||
| + | 0x1602 - Counter 2 Register | ||
| + | 0x1603 - Control Word Register | ||
| + | } | ||
| } | } | ||
| Line 99: | Line 137: | ||
| 0x1c00-0x1fff WRITE ONLY | 0x1c00-0x1fff WRITE ONLY | ||
| U820: { | U820: { | ||
| - | 0x1c00-0x1c7f L1* | + | 0x1c00-0x1c7f L1* RA1-RA6, NOT |
| - | 0x1c80-0x1cff L2* | + | 0x1c80-0x1cff L2* RB1-RB6 |
| - | 0x1d00-0x1d7f L3* | + | 0x1d00-0x1d7f L3* - SYNC1/ |
| 0x1d80-0x1dff MISC* | 0x1d80-0x1dff MISC* | ||
| $ U818 - 74LS174 - 6bit latch, address bank register { | $ U818 - 74LS174 - 6bit latch, address bank register { | ||
| Line 164: | Line 202: | ||
| {{ : | {{ : | ||
| + | ==== 82C54 Programmable Interval Timer ==== | ||
| + | {{ :82c54.pdf | Datasheet}} | ||
| + | ===== Using r2 ===== | ||
| + | To start radare2 on the image: | ||
| + | |||
| + | < | ||
| + | $ r2 -a mc6809 -m 0x8000 27256.bin | ||
| + | </ | ||
oberheimmatrix1000.1469858031.txt.gz · Last modified: 2016-07-30 05:53 by gde